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From chip design to the software that runs on top of it, here's where we need help right now.
Silicon Engineering
AI Accelerator Microarchitecture/RTL Engineer
Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)
Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)
Join our hardware team as a new grad or co-op working on core execution for our compute architecture, with hands-on ownership of functional blocks across the accelerator pipeline — from spec through RTL, verification, and bring-up.
What you'll do
- Own the design and implementation of functional blocks within the accelerator pipeline
- Write and debug RTL (Verilog/SystemVerilog) for your assigned block
- Collaborate with verification engineers to define test plans and close coverage
- Analyze performance, timing, and area tradeoffs and propose improvements
- Participate in design reviews and document your block's architecture and behavior
What we're looking for
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Recently completed coursework in computer microarchitecture, covering at least one of:
- Cache/memory systems
- Computer arithmetic
- Pipeline design
- Working knowledge of modern ISAs, such as:
- RISC-V
- ARM
- x86
- Familiarity with parallel accelerator architectures, such as:
- SIMD / SIMT / vector processing
- Out-of-order scheduling
- Hands-on Verilog/SystemVerilog experience, including:
- Simulation and testbench debugging
- Timing and power closure
- Understanding of the end-to-end ASIC design flow and general VLSI concepts
- Scripting experience (Python, Perl, or Tcl); C/C++ a plus
CPU Microarchitecture/RTL Engineer
Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)
Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)
Join our CPU hardware engineering team as a new grad or co-op and help build our next-generation high-performance processors — owning functional blocks across the CPU pipeline from microarchitecture through RTL, verification, and silicon bring-up.
What you'll do
- Design and implement CPU functional blocks based on microarchitecture specifications
- Develop, debug, and optimize RTL using SystemVerilog/Verilog
- Analyze performance, timing, area, and power tradeoffs and propose improvements
- Work with verification engineers to develop test plans and achieve functional coverage
- Partner with physical design engineers on area, timing, and power goals
- Participate in microarchitecture and RTL design reviews and write technical documentation
What we're looking for
- Bachelor's or Master's degree (or near-term graduation) in one of:
- Electrical Engineering
- Computer Engineering
- Computer Science
- A related field
- Strong foundation in computer architecture and digital design, with solid understanding of at least two of the following:
- Out-of-order execution
- CPU front-end / control logic
- Load/store and memory systems
- Cache hierarchy and coherency
- Virtual memory
- Floating-point / computer arithmetic
- SIMD / vector processing
- Working knowledge of a modern ISA (RISC-V, ARM, or x86)
- Hands-on Verilog/SystemVerilog experience, including:
- RTL simulation
- Testbench-based debugging
- Familiarity with the ASIC design flow:
- RTL design
- Verification
- Synthesis
- Timing analysis
- Scripting experience for automation, test generation, or data analysis, such as:
- Python
- C/C++
- Perl
- Tcl
Software Engineering
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Platform Engineering
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